Verilog Program for Real Time Clock

This Program is done in Quartus II & verified using Altera kit..

//main module

module rtc(clock,a,b,c,d,e,f,rst);

input clock,rst;

output[0:6]a,b,c,d,e,f;

wire [3:0]u,v,w,x;

wire [4:0]y;

bcdcascade(clock,u,v,w,x,y,rst);

bcdtoseven sec1(u,a);

bcdtoseven sec2(v,b);

bcdtoseven min1(w,c);

bcdtoseven min2(x,d);

fi_bi_seven(y,f,e);

endmodule

//bcdtoseven coding

module bcdtoseven(x,a);

input [3:0]x;

output [0:6]a;

reg [0:6]a;

always@(x)

case(x[3:0])

4’b0000:a=7’b0000001;

4’b0001:a=7’b1001111;

4’b0010:a=7’b0010010;

4’b0011:a=7’b0000110;

4’b0100:a=7’b1001100;

4’b0101:a=7’b0100000;

4’b0111:a=7’b0001111;

4’b1000:a=7’b0000000;

4’b1001:a=7’b0000100;

endcase

endmodule

//bcdcascaded coding

module bcdcascade(clock,u,v,w,x,y,rst);

input clock,rst;

output [3:0]u,v,w,x;

output [4:0]y;

wire ck;

fiftyone(clock,ck);

clktobcdmod10(ck,u,rst);

clktobcdmod6(u[3],v,rst);

clktobcdmod10(v[2],w,rst);

clktobcdmod6(w[3],x,rst);

hrcounter(x[2],y,rst);

endmodule

//time converter

module fiftyone(ck,q);

input ck;

output q;

wire x,y;

modthous(ck,x);

modthous(x,y);

modfif(y,q);

endmodule

//modulous thousand

module modthous(ck,x);

input ck;

output x;

reg [9:0]sig;

reg x;

initial sig=10’d0;

always@(posedge ck)

begin

sig=(sig+1)%1000;

x=sig[9];

end

endmodule

//Modulous fifty counter

module modfif(ck,x);

input ck;

output x;

reg [5:0]sig;

reg x;

initial sig=6’d0;

always@(posedge ck)

begin

sig=(sig+1)%50;

x=sig[5];

end

endmodule

//clock to bcdmod6

module clktobcdmod6(clock,x,rst);

input clock,rst;

output [3:0]x;

reg [3:0]x;

initial x=4’b0000;

always@(negedge clock or negedge rst)

if(rst==0)

x=4’b0000;

else

x=(x+1)%6;

endmodule

//clock to bcdmod10

module clktobcdmod10(clock,x,rst);

input clock,rst;

output [3:0]x;

reg [3:0]x;

initial x=4’b0000;

always@(negedge clock or negedge rst)

if(rst==0)

x=4’b0000;

else

x=(x+1)%10;

endmodule

//coding for hour counter

module hrcounter(clock,x,rst);

input clock,rst;

output reg [4:0]x;

initial x=5’b00000;

always@(negedge clock or negedge rst)

if(rst==0)

x=5’b00000;

else

x=(x+1)%24;

endmodule

//coding for segment decoder

module fi_bi_seven(x,y,z);

input [4:0]x;

output reg [6:0]y,z;

always@(x)

case(x)

5’d0:begin

y=7’b0000001;

z=7’b0000001;

end

5’d1:begin

y=7’b0000001;

z=7’b1001111;

end

5’d2:begin

y=7’b0000001;

z=7’b0010010;

end

5’d3:begin

y=7’b0000001;

z=7’b0000110;

end

5’d4:begin

y=7’b0000001;

z=7’b1001100;

end

5’d5:begin

y=7’b0000001;

z=7’b0100100;

end

5’d6:begin

y=7’b0000001;

z=7’b0100000;

end

5’d7:begin

y=7’b0000001;

z=7’b0001111;

end

5’d8:begin

y=7’b0000001;

z=7’b0000000;

end

5’d9:begin

y=7’b0000001;

z=7’b0000100;

end

5’d10:begin

y=7’b1001111;

z=7’b0000001;

end

5’d11:begin

y=7’b1001111;

z=7’b1001111;

end

5’d12:begin

y=7’b1001111;

z=7’b0010010;

end

5’d13:begin

y=7’b1001111;

z=7’b0000110;

end

5’d14:begin

y=7’b1001111;

z=7’b1001100;

end

5’d15:begin

y=7’b1001111;

z=7’b0100100;

end

5’d16:begin

y=7’b1001111;

z=7’b0100000;

end

5’d17:begin

y=7’b1001111;

z=7’b0001111;

end

5’d18:begin

y=7’b1001111;

z=7’b0000000;

end

5’d19:begin

y=7’b1001111;

z=7’b0000100;

end

5’d20:begin

y=7’b0010010;

z=7’b0000001;

end

5’d21:begin

y=7’b0010010;

z=7’b1001111;

end

5’d22:begin

y=7’b0010010;

z=7’b0010010;

end

5’d24:begin

y=7’b0010010;

z=7’b1001100;

end

endcase

endmodule

2 thoughts on “Verilog Program for Real Time Clock

  1. Selvariyan Natarajan March 4, 2012 / 5:15 PM

    Could you please explain the logic for this real time clock program???….

    • SURYA March 11, 2012 / 3:36 AM

      Thank You for visiting, I will update the content very soon..!!

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